Semiconductor memory devices are subject to defects that may cause some memory cells to be read with incorrect data. Such defects are generally discovered during post-manufacture testing of integrated circuit memory devices. Defective memory devices may need to be discarded, thereby reducing the yield of the integrated circuit manufacturing process, and increasing the net manufacturing costs for the non-defective devices.
A number of techniques are known for configuring a memory device to remain operative in the presence of defects. One such technique involves incorporating redundant lines, rows or blocks of cells into the device. This allows lines, rows or blocks having defective cells to be replaced with corresponding non-defective redundant elements. Volatile or non-volatile switching elements may be used to implement the replacement.
Another technique for dealing with defects in memory devices involves utilizing error correction coding (ECC) to correct data errors attributable to defects. Examples of this type of approach are disclosed in U.S. Patent Application Publication No. 2006/0048031, entitled “Built-In Self-Test for Memory Arrays Using Error Correction Coding,” which is commonly assigned herewith and incorporated by reference herein.
It is generally desirable to support partial word write operations on memory devices that include error correction capability. A partial word write operation occurs when one or more, but not all, of the bits in a word are to be written. The remaining bits in the word are not changed but remain at their previous values. Examples of partial word write operations include byte write operations and bit write operations.
Memory devices that incorporate ECC typically require two cycles of an external clock to perform a partial word write operation, namely, a first cycle for a read phase of the partial word write operation and a second cycle for a write phase of the partial word write operation. Requiring two clock cycles is disadvantageous because it slows down the data transfer rate between the memory device and a higher-level system that incorporates or otherwise utilizes that device. For example, two external cycles may be used to perform a given partial word write operation. However, this approach slows the data transfer rate by a factor of two, by requiring a no-operation (NOOP) cycle following the cycle that initiates the partial word write operation. Alternatively, the external cycle time specification for the memory device may be increased by a factor of two, and thus its external clock frequency may be reduced by a factor of two to allow time for the two cycles to occur internally to the device. Unfortunately, this approach also slows the data transfer rate by a factor of two.
A number of techniques are known in the art for reducing the time needed to perform a partial word write operation in a memory device that incorporates ECC. These techniques generally allow the write phase of the partial word write operation to be accomplished in a time somewhat shorter than a full cycle, and thus the partial word write operation can be executed in somewhat less than two cycles.
One such technique is disclosed in U.S. Patent Application Publication No. 2006/0112321, entitled “Transparent Error Correcting Memory That Supports Partial-Word Write,” which is incorporated by reference herein. This technique involves keeping particular sense amplifiers and rows of the memory device active from the read phase through the write phase, whereas normally they would have been deactivated at the end of the read phase and reactivated at the beginning of the write phase.
Another technique for reducing the time needed to perform a partial word write operation is referred to as predictive ECC, and is described in U.S. Patent Application Publication No. 2006/0123322, entitled “Predictive Error Correction Code Generation Facilitating High-Speed Byte-Write in a Semiconductor Memory,” which is incorporated by reference herein. This technique allows ECC decode of a read word to be performed at the same time as ECC encode of the word to be written, thereby reducing the overall time required to complete the partial word write operation.
In the predictive ECC technique, the elapsed time for a partial word write operation is reduced by an amount given by the shorter of (i) the combined duration of an ECC decode process and its associated correct process, and (ii) the duration of an ECC encode process. Typically, the duration of the ECC encode process is shorter than the combined duration of the ECC decode and correct processes, and thus the improvement provided by the predictive ECC technique is limited to the duration of the shorter ECC encode process. The ECC decode and correct processes remain in the critical timing path of the partial word write operation.
Accordingly, a need exists for an improved approach to performing partial word write operations in memory devices with error correction capability.